The present invention relates to field effect transistors, and more particularly to a pentode field effect transistor.
Field effect transistors, (FET) conventionally, are three terminal devices having source and drain regions formed on an upper surface of a semiconductor wafer and interconnected by a channel region, and a gate region overlying the channel region which controls current flow through the channel. The FET operates on a principle different from that of the conventional transistor. Briefly, the FET consists of a bar of semiconductor material, the resistance of which is modulated by varying the effective cross-sectional area of the bar by electrical means. A layer of high resistivity (semi-insulating) semiconductor material is utilized to support a layer of low resistivity semiconductor material which is grown on the first layer by several well known means. The low resistivity layer is contacted at one end by an ohmic contact, referred to as a source, and at the other end by an ohmic contact referred to as a drain. The conduction current to be modulated is carried between the source and drain contacts. The gate contact is typically, but not necessarily, a Schottky-barrier deposited upon the low resistivity layer and so disposed that the cross-sectional area available for conduction between the source and the drain is a function of the magnitude of the bias potential existing between gate and source. In the fabrication of FET's, it has been found necessary to avoid overlap between the drain region and the gate electrode to reduce the well known Miller-type capacitance in order to increase the freqeuncy of the device.
Recently, with the improvement in gallium arsenide (GaAs) technology and the refinement of pattern definition and etching techniques, GaAs field effect transistors with very small gate lengths have been produced. The use of such devices in amplifiers permits good gain and noise properties through the X and K.sub.u frequency bands, with usable gain to 20 gigahertz, for example.
The use of computer aided design techniques has considerably eased the problem of realizing both broad and narrow band microwave amplifier design. However, the high input and output impedance of the FET presents a major design problem, particularly at the lower microwave frequencies, such as in L band. Also, acceptable match requirements can limit the usable bandwidth. The problems encountered in using the FET involve the gate-to-drain capacitance similar to the grid-to-plate capacitor of a vacuum triode which was so great that oscillation, could occur whenever the load resistance was made large enough to provide useful voltage amplification. Thus, the resulting feedback is difficult to handle.
The problem of grid-to-plate capacitance was originally attacked by the use of the vacuum pentode, which tube provided a higher output impedance with lower interelectrode capacitances; and in particular, a much reduced grid-to-plate feedback capacitance. This resulted in a much improved gain-bandwidth product and a higher frequency to which the tube could be used in the grid input, grounded cathode configuration. The penalty was the increased noise figure inherent with the pentode because of the added noise arising due to partitioning (partition noise) of the cathode current between the plate and the screen.
To overcome the disadvantages of the vacuum pentode, it was proposed to provide a two stage amplifier comprising a pair of vacuum triodes in cascade arrangement, which could be considered analogous to a cascade arrangement of two conventional FET's. Refer to FIG. 1, which shows two conventional field effect transistors 10 and 11 connected in the well known Wallman arrangement. A source 12 of the FET 10 is connected to signal ground. The drain 13 of the FET 10 is signal connected to source 15 of the FET 11. The FET 11 is connected "grounded gate" in that gate 17 is signal connected to ground; and the amplified signal travels from drain 16 of the FET 11 to a load designated B. The signal input is at point A and connects to gate 14 of the FET 10. The feedback from the drain 13 of the FET 10 to the gate 14 connected to the input A causes a special effect commonly called the "Miller effect." This effect is produced by the gate 14 to drain 13 interelectrode capacitance, referred to as C.sub.gp. Because the voltage at the drain 13 drops by K volts for each volt rise at gate 14 (where K is the voltage gain of the FET 10), the capacitive current flowing into the gate 14 is of a magnitude which would be caused by a capacitor of magnitude (K + 1) C.sub.gp if it were connected from the gate 14 to ground. Thus the effect is to cause unwanted capacitive loading of the input A if the voltage gain K is of a useful level.
With respect to the cascade arrangement of the prior art FIG. 1, assuming that the two FET's 10 and 11 are identical, and each has a transconductance G.sub.m ; the voltage gain K.sub.AB from the input A to the output B is approximately given by K.sub.AB = G.sub.m R.sub.B, where R.sub.B is the load at point B. It is well known that K.sub.AB can be made a reasonable and useful magnitude. Also, the load resistance presented by the source 15 to the drain 13 is well approximated by 1/G.sub.m and thus the voltage gain of the first stage is approximately unity. If a single FET were used to obtain the full gain K.sub.AB, the additional input capacitance loading is C.sub.gp (K.sub.AB +1). The cascade or Wallman circuit configuration, is such that the additional loading is 2C.sub.gp. Thus there is a reduction of the effective loading by a ratio (1/2) (K.sub.AB +1)1.
Thus, it is desirable to provide a field effect transistor which has performance substantially better than that attainable with the conventional single field effect transistor devices, such as a better gain-bandwidth product, lower noise figure, higher input impedance, and high RF power handling capability. Also, it is desirable to provide in such single improved device all of the benefits afforded by the well known cascade arrangement of separate FET devices.